This invention relates to programmable logic devices, and more particularly, to optimizing logic designs for programmable logic devices by taking into account the effects of congestion.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools use information on the hardware capabilities of a given programmable logic device to help the designer implement the custom logic circuit using the resources available on that given programmable logic device. To ensure that the customized programmable logic device performs satisfactorily, the computer-aided design tools optimize the placement and routing of resources on the device.
As semiconductor fabrication methods improve, it is becoming possible to fabricate transistors and other integrated circuit components with increasingly small dimensions. It is generally desirable to shrink component sizes and otherwise scale devices as much as possible to reduce costs and improve performance. However, as devices become smaller, the effects of circuit congestion become increasingly important to consider.
Congestion can lead to a number of problems. If circuits are spaced too closely or if too many components are active, the power supply voltage on certain power supply lines may droop due to current loading effects. Local heating can give rise to hotspots on a device, which can adversely affect circuit performance. Sometimes signals interact poorly with each other and produce crosstalk.
With conventional programmable logic device CAD tools, designs are optimized during placement and routing operations by considering resistance-capacitance (RC) circuit delay effects. Using this type of information, a conventional programmable logic device CAD tool may decide to move certain portions of logic on a programmable logic device to improve performance. If, for example, a certain block of logic must frequently access a hardwired multiplier circuit and a memory, the CAD tool can place that block of logic adjacent to the multiplier circuit and the memory, thereby reducing interconnect delays.
However, programmable logic device CAD tools do not adequately address the effects of congestion. For example, while it may be possible to estimate the operating temperature of a programmable logic device, existing tools are not able to identify hotspots or areas where supply voltages droop due to signal loading. It may be possible to estimate cross-talk noise on certain nodes in a circuit with existing tools, but existing tools are not able to optimize a circuit to reduce cross-talk problems. Moreover, it is not possible to use custom-logic or application-specific integrated circuit (ASIC) design tools to address these issues, because those tools are incapable of creating custom logic designs for programmable logic devices.
It would therefore be desirable to be able to optimize programmable logic device designs by taking into account the effects of circuit congestion.